During logic synthesis, logic cells from a cell library are mapped into a netlist to begin the physical design process of an integrated circuit. In order that logical computations can be made within a given clock period, logic gates in a data path are often separated by D-type flip flops during the logic synthesis process. Oftentimes the logic gates are conservatively placed between D-type flip flops such that the timing delays can easily beat out the given clock period. However, this leads to overly conservative designs that are not area efficient. Retiming the logic gates in a data path by moving the flip flops forward or backward to eliminate one or more flip flops can conserve area in an integrated circuit design that can lead to a reduced die size with reduced manufacturing costs.
It is also difficult to predict the delay of logic gates that realize a logic function. In this case, retiming is used to improve the performance (e.g., cycle time) of the integrated circuits.
As integrated circuits have become more complex, it has become more difficult to perform retiming, requiring additional time to complete the retiming process in the design flow of integrated circuits.
It is desirable to improve the efficiency of the retiming process so that it is performed more quickly to improve productivity of the integrated circuit design process.